1. Field of the Invention
The present patent application relates to a memory device having a duty ratio corrector, and more particularly to, a memory device having a duty ratio corrector which can minimize power consumption and rapidly generate an output signal by blocking current paths in an initial mode.
2. Discussion of Related Art
All memory devices use clock signals. As an operational speed of the memory device increases, a duty ratio of an input clock signal influences performance of the whole chip. Therefore, a duty ratio corrector for maintaining a duty ratio of a clock signal at 50% has been employed.
The operation of the duty ratio corrector will now be described.
FIG. 1 is a concept diagram for explaining the operation of the general duty ratio corrector.
Referring to FIG. 1, the duty ratio corrector basically includes two resistance devices R101 and R102, two switching devices N101 and N102, a current supply means I101 and two capacitors C101 and C102. The coupling structure of the duty ratio corrector will now be explained in more detail.
The first resistance device R101 is coupled between a power voltage terminal VDD and a first output terminal OUT1. The second resistance device R102 is coupled between the power voltage terminal VDD and a second output terminal OUT2. Here, the first and second resistance devices R101 and R102 have the same resistance value.
The first switching device N101 is coupled to the first resistance device R101 and operated according to an inverted clock signal clkb. The second switching device N102 is coupled to the second resistance device R102 and operated according to a clock signal clk.
The current supply means I101 is coupled between the first and second switching devices N101 and N102 and a ground terminal GND, so that a constant current can regularly flow through the first and second resistance devices R101 and R102.
The first capacitor C101 is coupled between the first output terminal OUT1 and the ground terminal GND. When the first switching device N101 is turned on, the first capacitor C101 is charged or discharged by the current flowing through the first resistance device R101 by the current supply means I101. The second capacitor C102 is coupled between the second output terminal OUT2 and the ground terminal GND. When the second switching device N102 is turned on, the second capacitor C102 is charged or discharged by the current flowing through the second resistance device R102 by the current supply means I101.
The operation of the duty ratio corrector will now be described.
FIGS. 2A to 2E are waveform diagrams for explaining the operation of the duty ratio corrector of FIG. 1.
As shown in FIG. 2A, when the clock signal clk is inputted in a higher level than a reference voltage Vref for deciding a high level and a low level and when the inverted clock signal clkb is inputted in a lower level than the reference voltage Vref, as shown in FIG. 2B, a rate of a high level pulse to a low level pulse of a clock pulse clkp or an inverted clock pulse clkpb is changed. In this case, an operational margin is sufficient in a high level but deficient in a low level to generate errors.
When receiving the clock signals clk and clkb, the duty ratio corrector increases the level of the clock signal clk and decreases the level of the inverted clock signal clkb, thereby correcting the rate of the high to low level. This operation will now be explained in more detail.
When the inverted clock signal clkb is inputted to the first switching device N101 in a high level, a turn-on time of the first switching device N101 gets longer than a turn-off time thereof. Accordingly, a time of flowing the current through the first resistance device R101 is relatively long, and thus the first capacitor C101 is more charged than discharged. As depicted in FIG. 2C, a level of a first auxiliary voltage DCC outputted to the first output terminal OUT1 gradually increases. The first auxiliary voltage DCC is added to the inverted clock signal clkb, and thus the level of the inverted clock signal clkb increases as shown in FIG. 2D.
On the other hand, when the clock signal clk is inputted to the second switching device N102 in a low level, a turn-off time of the second switching device N102 gets longer than a turn-on time thereof. Accordingly, a time of flowing the current through the second resistance device R102 is relatively short, and thus the second capacitor C102 is more discharged than charged. As depicted in FIG. 2C, a level of a second auxiliary voltage DCCB outputted to the second output terminal OUT2 gradually decreases. The second auxiliary voltage DCCB is added to the clock signal clk, and thus the level of the clock signal clk decreases as shown in FIG. 2D.
When the level of the clock signal clk decreases and the level of the inverted clock signal clkb increases by the above operation, as shown in FIG. 2E, an intermediate level between the clock signal clk and the inverted clock signal clkb is identical to the level of the reference voltage Vref, and thus the rate of the high to low level is the same.
As described above, the duty ratio corrector is operated according to the clock signal clk and the inverted clock signal clkb which have opposite phases. When receiving the opposite phase signals at the same time, any one of the first switching device N101 and the second switching device N102 must be turned on. Therefore, the current starts to flow in a standby mode or before a normal operation mode, which results in high power consumption.
In addition, when one of the first switching device N101 and the second switching device N102 is turned on, any one of the first auxiliary voltage DCC and the second auxiliary voltage DCCB is outputted as 0V. In order to perform a normal operation, 0V of auxiliary voltage DCC or DCCB must be increased to an target level. However, it takes a long time to increase the auxiliary voltage DCC or DCCB to the target level, and thus takes a long time to correct the duty ratio. As a result, it influences a lock time of a delay locked loop using the same.